Technical Field
The present invention relates generally to architectures for serial data link transmitters employing pulse amplitude modulation (PAM) and, in particular, to 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases.
Description of the Related Art
Demands for high-bandwidth data transmission continues to increase for systems such as servers and high-speed routers. Non-return-to-zero (NRZ) modulation has been commonly employed in such data communication links. In NRZ systems, a single bit of information is conveyed in each data symbol transmitted. This has historically been preferred in many electrical links over other modulation schemes such as pulse amplitude modulation. In 4-level pulse amplitude modulation (PAM-4) serial links, two bits of information are conveyed in each data symbol. This results in better spectral efficiency than NRZ data transmission which is advantageous when transmitted over bandwidth linked channels. However, for a given maximum transmit amplitude, this results in a 9.5-dB reduction in the transmitted signal-to-noise ratio (SNR) as compared to NRZ data. A modern serial link may employ feed-forward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization, or any combination of these three equalization techniques. These equalization techniques remove inter-symbol interference (ISI) from data transmitted over bandwidth limited channels, making it easier for the receiver to detect the transmitted bit. This is particularly true if the transmitted data symbol has a high inherent SNR, favoring NRZ signaling over PAM signaling.
Despite its SNR advantage, the increased symbol rate is still a drawback for NRZ signaling as compared to PAM-4. One concern lies in the generation of high-quality, high-frequency clocks for serial transceivers. Random jitter specifications for a Phase Locked Loop (PLL) must be tightened as the symbol rate increases, favoring PAM signaling. To date PAM-4 transmitter architectures have employed a “half-rate” architecture meaning that one symbol is transmitted on every rising and falling edge of a C2 (half-rate) clock. As an example, for 56 Gb/s PAM4 data transmission, the symbol rate is 28Gbaud, and a half-rate transmitter architecture would require a 14 GHz C2 clock (presumable, two complimentary or differential clock signals). Distribution of these high-frequency clocks may be challenging.